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data sheet 0 8.95 mi c r o c omp u ter componen t s s a b 80c 5 1 5 a / 8 3 c5 15a-5 8-bit cmos single-chip microcontroller
semiconductor group 1 08.95 high-performance sab 80c515a / 83c515a-5 8-bit cmos single-chip microcontroller preliminary sab 83c515a-5 microcontroller with factory mask-programmable rom sab 80c515a microcontroller for external rom l sab 80c515a / 83c515a-5, up to 18 mhz operation frequency l 32 k 8 rom (sab 83c515a-5 only, rom-protection available) l 256 8 on-chip ram l additional 1 k 8 on-chip ram (xram) l superset of sab 80c51 architecture: 1 m s instruction cycle time at 12 mhz 666 ns instruction cycle time at 18 mhz 256 directly addressable bits boolean processor 64 kbyte external data and program memory addressing l three 16-bit timer/counters l versatile "fail-safe" provisions l twelve interrupt vectors, four priority levels selectable l genuine 10-bit a/d converter with 8 multiplexed inputs l full duplex serial interface with programmable baudrate-generator l functionally compatible with sab 80c515 l extended power saving mode l fast power-on reset l seven ports: 48 i/o lines, 8 input lines l two temperature ranges available: 0 to 70 c (t1) ?40 to 85 c (t3) l plastic packages: p-lcc-68 and p-mqfp-80 the sab 80c515a/83c515a-5 is a high-end member of the siemens sab 8051 microcontroller family. it is designed in siemens acmos technology and based on the sab 8051 architecture. acmos is a technology which combines high-speed and density characteristics with low-power consumption or dissipation. while maintaining all the sab 80c515 features and operating characteristics the sab 80c515a/83c515a-5 contains more on-chip ram/rom. furthermore a new 10-bit a/d- converter is implemented as well as extended security mechanisms. the sab 80c515a is identical with the sab 83c515a-5 except that it lacks the on-chip program memory. the sab 80c515a / 83c515a-5 is supplied in a 68-pin plastic leaded chip carrier package (p-lcc- 68) and in a 80-pin plastic metric quad flat package (p-mqfp-80). versions for extended temperature range ?40 to + 110 c are available on request.
sab 80c515a/83c515a-5 semiconductor group 2 ordering information notes : versions for extended temperature range - 40 to + 110 c on request. the ordering number of rom types (dxxxx extension) is defined after program release (verification) of the customer. type ordering code package description 8-bit cmos microcontroller sab 80c515a-n18 q67120-c0581 p-lcc-68 for external memory, 18 mhz sab 83c515a-5n18 q67120-dxxxx p-lcc-68 with mask-programmable rom, 18 mhz sab 80c515a-n18-t3 q67120-c0784 p-lcc-68 for external memory, 18 mhz ext. temperature - 40 to + 85 c sab 83c515a-5n18-t3 q67120-dxxxx p-lcc-68 with mask-programmable rom, 18 mhz ext. temperature - 40 to + 85 c sab 80c515a-m18-t3 q67120-c0851 p-mqfp-80 for external memory, 18 mhz ext. temperature - 40 to + 85 c sab 83c515a-5m18-t3 q67120-dxxxx p-mqfp-80 with mask-programmable rom, 18 mhz ext. temperature - 40 to + 85 c
sab 80c515a/83c515a-5 semiconductor group 3 logic symbol
sab 80c515a/83c515a-5 semiconductor group 4 the pin functions of the sab 80c515a are identical with those of the sab 80c515 with following exception: pin configuration (p-lcc-68) pin sab 80c515a sab 80c515 68 1 4 hwpd p0.4/adst pe /swd v cc p4.0 pe
sab 80c515a/83c515a-5 semiconductor group 5 pin configuration (p-mqfp-80 ) n.c. pins must not be connected. p0.6 / ad6 sab 80c515a / 80c515a-5 80 1 5 10 15 20 21 25 30 40 41 35 45 50 55 60 61 65 70 75 p0.7 / ad7 p0.5 / ad5 p0.4 / ad4 p0.2 / ad2 p0.3 / ad3 p0.1 / ad1 p0.0 / ad0 p5.7 n.c. ea ale psen p2.7 / a15 n.c. n.c. p2.6 / a14 p2.5 / a13 p2.4 / a12 p2.3 / a11 varef n.c. vagnd p6.7 / ain7 p6.5 / ain5 p6.6 / ain6 p6.4 / ain4 p6.3 / ain3 reset p6.2 / ain2 p6.0 / ain0 n.c. n.c. p3.1 / txd0 p6.1 / ain1 p3.0 / rxd0 p3.2 / int0 p3.3 / int1 p3.4 / t0 p3.5 / t1 n.c. p3.7 / rd p1.7 / t2 p1.6 / clkout p1.4 / int2 p1.5 / t2ex p1.3 / int6 / cc3 p1.2 / int5 / cc2 p3.6 / wr p1.1 / int4 / cc1 vcc vcc vss xtal2 p1.0 / int3 / cc0 vss xtal1 p2.0 / a8 p2.1 / a9 p2.2 / a10 p4.5 p4.6 p4.4 p4.3 p4.2 pe / swd p4.1 p4.0 / adst p4.7 n.c. hwpd n.c. p5.0 p5.2 n.c. p5.1 p5.3 p5.4 p5.5 p5.6
sab 80c515a/83c515a-5 semiconductor group 6 pin definitions and functions symbol pin p-lcc-68 pin p-mqfp-80 input (i) output (o) function p4.0-p4.7 1-3, 5-9 72-74, 76-80 i/o port 4 is an 8-bit bidirectional i/o port with internal pull-up resistors. port 4 pins that have 1? writ- ten to them are pulled high by the internal pull- up resistors, and in that state can be used as inputs. as inputs, port 4 pins being externally pulled low will source current ( i il , in the dc characteristics) because of the internal pull-up resistors. p4 also contains the external a/d converter control pin. the output latch corresponding to a secondary function must be programmed to a one (1) for that function to operate. the sec- ondary function assigned to port 6: ? adst (p4.0): external a/d converter start pin pe /swd 4 75 i power saving mode enable /start watch- dog timer a low level on this pin allows the software to enter the power down, idle and slow down mode. in case the low level is also seen during reset, the watchdog timer function is off on de- fault. use of the software controlled power saving modes is blocked, when this pin is held on high level. a high level during reset performs an automatic start of the watchdog timer im- mediately after reset. when left unconnected this pin is pulled high by a weak internal pull-up resistor. reset 10 1 i reset pin a low level on this pin for the duration of two machine cycles while the oscillator is running resets the sab 80c515a. a small internal pullup resistor permits power-on reset using only a capacitor connected to v ss v aref1 11 3 reference voltage for the a/d converter v agnd 12 4 reference ground for the a/d converter
sab 80c515a/83c515a-5 semiconductor group 7 p6.7-p6.0 13-20 5-12 i port 6 is an 8-bit unidirectional input port to the a/ d converter. port pins can be used for digital input, if voltage levels simultaneously meet the specifications high/low input voltages, and for the eight multiplexed analog inputs. p3.0-p3.7 21-28 15-22 i/o port 3 is an 8-bit bidirectional i/o port with internal pullup resistors. port 3 pins that have1's written to them are pulled high by the internal pullup resistors, and in that state can be used as inputs. as inputs, port 3 pins being externally pulled low will source current ( i il , in the dc characteristics) because of the internal pullup resistors. port 3 also contains the interrupt, timer, serial port and external memory strobe pins that are used by various options. the output latch corresponding to a secondary function must be programmed to a one (1) for that function to operate. the secondary functions are assigned to the pins of port 3, as follows: ? d (p3.0): serial port? receiver data input (asynchronous) or data input/output (synchronous) ? d (p3.1): serial port? transmitter data output (asynchronous) or clock output (synchronous) int0 (p3.2): interrupt 0 input/timer 0 gate control input int1 (p3.3): interrupt 1 input/timer 1 gate control input t0 (p3.4): counter 0 input t1 (p3.5): counter 1 input ?r (p3.6): the write control signal latches the data byte from port 0 into the external data memory ?d (p3.7): the read control signal enables the external data memory to port 0 pin definitions and functions (cont?) symbol pin p-lcc-68 pin p-mqfp-80 input (i) output (o) function
sab 80c515a/83c515a-5 semiconductor group 8 p1.7 - p1.0 29-36 24-31 i/o port 1 is an 8-bit bidirectional i/o port with internal pullup resistors. port 1 pins that have 1's written to them are pulled high by the internal pullup resistors, and in that state can be used as inputs. as inputs, port 1 pins being externally pulled low will source current ( i il in the dc characteristics) because of the internal pullup resistors. the port is used for the low- order address byte during program verification. port 1 also contains the interrupt, timer, clock, capture and compare pins that are used by various options. the output latch corresponding to a secondary function must be programmed to a one (1) for that function to operate (except when used for the compare functions). the secondary functions are assigned to the port 1 pins as follows: int3 /cc0 (p1.0): interrupt 3 input / compare 0 output / capture 0 input int4/cc1 (p1.1): interrupt 4 input / compare 1 output / capture 1 input int5/cc2 (p1.2): interrupt 5 input / compare 2 output / capture 2 input int6/cc3 (p1.3): interrupt 6 input / compare 3 output / capture 3 input int2 (p1.4): interrupt 2 input t2ex (p1.5): timer 2 external reloadtrigger input clkout (p1.6): system clock output t2 (p1.7): counter 2 input xtal2 39 36 xtal2 input to the inverting oscillator amplifier and input to the internal clock generator circuits. pin definitions and functions (cont?) symbol pin p-lcc-68 pin p-mqfp-80 input (i) output (o) function
sab 80c515a/83c515a-5 semiconductor group 9 xtal1 40 37 - xtal1 output of the inverting oscillator amplifier. to drive the device from an external clock source, xtal2 should be driven, while xtal1 is left unconnected. there are no require- ments on the duty cycle of the external clock signal, since the input to the internal clok- king circuitry is divided down by a divide-by- two flip-flop. minimum and maximum high and low times and rise/fall times specified in the ac characteristics must be taken into account. p2.0-p2.7 41-48 38-45 i/o port 2 is an 8-bit bidirectional i/o port with internal pullup resistors. port 2 pins that have 1's written to them are pulled high by the internal pullup resistors, and in that state can be used as inputs. as inputs, port 2 pins being externally pulled low will source current ( i il, in the dc characteristics) because of the internal pullup resistors. port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (movx@dptr). in this application it uses strong internal pullup resistors when issuing 1's. during accesses to external data memory that use 8-bit addresses (movx@ri), port 2 issues the contents of the p2 special function register. psen 49 47 o the program store enable output is a control signal that enables the external program memory to the bus during external fetch operations. it is activated every six oscillator periods, except during external data memory accesses. the signal remains high during internal program execution. ale 50 48 o the address latch enable output is used for latching the address into external memory during normal operation. it is activated every six oscillator periods, except during an external data memory access. pin definitions and functions (cont?) symbol pin p-lcc-68 pin p-mqfp-80 input (i) output (o) function
sab 80c515a/83c515a-5 semiconductor group 10 ea 51 49 i external access enable when held high, the sab 80c515a executes instructions from the internal rom as long as the pc is less than 32768. when held low, the sab 80c515a fetches all instructions from external program memory. for the sab 80c515a this pin must be tied low. p0.0-p0.7 52-59 52-59 i/o port 0 is an 8-bit open-drain bidirectional i/o port. port 0 pins that have 1's written to them float, and in that state can be used as high- impedance inputs. port 0 is also the multiplexed low-order address and data bus during accesses to external program and data memory. in this application it uses strong internal pullup resistors when issuing 1's. port 0 also outputs the code bytes during program verification in the sab 80c515a. external pullup resistors are required during program verification. p5.7-p5.0 60-67 60-67 i/o port 5 is an 8-bit bidirectional i/o port with internal pullup resistors. port 5 pins that have 1's written to them are pulled high by the internal pullup resistors, and in that state can be used as inputs. as inputs, port 5 pins being externally pulled low will source current ( i il in the dc characteristics) because of the internal pullup resistors. hwpd 68 69 i har d ware p o wer do wn a low level on this pin for the duration of one machine cycle while the oscillator is running resets the sab 80c515a. a low level for a longer period will force the part to power down mode with the pins float- ing. ( see table 5 ) v cc 37 32, 33 supply voltage during normal, idle, and power-down operation. v ss 38 34, 35 ground (0 v) n.c. 2, 13, 14, 23, 46, 50, 51, 68, 70, 71 not connected these pins of the p-mqfp-80 package must not be connected. pin definitions and functions (cont?) symbol pin p-lcc-68 pin p-mqfp-80 input (i) output (o) function
sab 80c515a/83c515a-5 semiconductor group 11 figure 1 block diagram
sab 80c515a/83c515a-5 semiconductor group 12 functional description the sab 80c515a is based on 8051 architecture. it is a fully compatible member of the siemens sab 8051/80c51 microcontroller family being an significantly enhanced sab 80c515. the sab 80c515a is therefore code compatible with the sab 80c515. having an 8-bit cpu with extensive facilities for bit-handling and binary bcd arithmetics the sab 80c515a is optimized for control applications. with a 18 mhz crystal, 58 % of the instructions are executed in 666.67 ns. while maintaining all architectural and operational characteristics of the sab 80c515 the sab 80c515a incorporates more on-chip ram. a new 10-bit a/d-converter is implemented as well as an oscillator watchdog unit. also the maximum operating frequency of 18 mhz is higher than at the sab 80c515. with exception of the rom sizes both parts are identical. therefore the therm sab 80c515a refers to both versions within this specification unless otherwise noted. memory organisation according to the sab 8051 architecture, the sab 80c515a has separate address spaces for program and data memory. figure 2 illustrates the mapping of address spaces. figure 2 memory map
sab 80c515a/83c515a-5 semiconductor group 13 program memory ('code space') the sab 83c515a-5 has 32 kbyte of on-chip rom, while the sab 80c515a has no internal rom. the program memory can externally be expanded up to 64 kbyte. pin ea determines whether program fetches below address 8000 h are done from internal or external memory. as a new feature the sab 83c515a-5 offers the possibility of protecting the internal rom against unauthorized access. this protection is implemented in the rom-mask. therefore, the decision rom-protection 'yes' or 'no' has to be made when delivering the rom-code. once enabled, there is no way of disabling the rom-protection. effect: the access to internal rom done by an externally fetched movc instruction is disabled. nevertheless, an access from internal rom to external rom is possible. to verify the read protected rom-code a special rom-verify-mode is implemented. this mode also can be used to verify unprotected internal rom. rom -protection rom-verification mode (see 'ac characteristics') restrictions no rom-verification mode 1 (standard 8051 verification mode) rom-verification mode 2 yes rom-verification mode 2 standard 8051 verification mode is disabled externally applied movc accessing internal rom is disabled
sab 80c515a/83c515a-5 semiconductor group 14 data memory ('data space') the data memory space consists of an internal and an external memory space.the sab 80c515a contains another 1 kbyte on on-chip ram additional to the 256-bytes internal ram of the base type sab 80c515. this ram is called xram ('extended ram') in this document. external data memory up to 64 kbyte external data memory can be addressed by instructions that use 8-bit or 16-bit indirect addressing. for 8-bit addressing movx instructions in combination with registers r0 and r1 can be used. a 16-bit external memory addressing is supported by a 16-bit datapointer. registers xpage and syscon are controlling whether data fetches at addresses f800 h to fbff h are done from internal xram or from external data memory. internal data memory the internal data memory is divided into four physically distinct blocks: the lower 128 bytes of ram including four register banks containing eight registers each the upper 128 byte of ram the 128 byte special function register area. a 1 k 8 area which is accessed like external ram (movx-instructions), implemented on chip at the address range from f800 h to fbff h . special function register syscon controls whether data is read from or written to xram or external ram. a map of the internal data memory is shown in figure 2. the overlapping address spaces of the standard internal data memory (256 byte) are accessed by different addressing modes (see user's manual sab 80c515). the stack can be located anywhere in the internal data memory. architecture of the xram the contents of the xram is not affected by a reset or hw power down. after power-up the contents is undefined, while it remains unchanged during and after a reset or hw power down if the power supply is not turned off. the additional on-chip ram is logically located in the "external data memory" range at the upper end of the 64 kbyte address range (f800 h -fbff h ). nevertheless when xram is enabled the address range f800 h to ffff h is occupied. this is done to assure software compatibility to sab 80c517a. it is possible to enable and disable (only by reset) the xram. if it is disabled the device shows the same behaviour as the parts without xram, i.e. all movx accesses use the external bus to physically external data memory.
sab 80c515a/83c515a-5 semiconductor group 15 accesses to xram because the xram is used in the same way as external data memory the same instruction types must be used for accessing the xram. note: if a reset occurs during a write operation to xram, the effect on xram depends on the cycle which the reset is detected at (movx is a 2-cycle instruction): reset detection at cycle 1: the new value will not be written to xram. the old value is not affected. reset detection at cycle 2: the old value in xram is overwritten by the new value. accesses to xram using the dptr there are a read and a write instruction from and to xram which use one of the 16-bit dptr for indirect addressing. the instructions are: movx a, @dptr (read) movx @dptr, a (write) normally the use of these instructions would use a physically external memory. however, in the sab 80c515a the xram is accessed if it is enabled and if the dptr points to the xram address space (dptr 3 f800 h ). accesses to xram using the registers r0/r1 the 8051 architecture provides also instructions for accesses to external data memory range which use only an 8-bit address (indirect addressing with registers r0 or r1). the instructions are: movx a, @ri (read) movx @ri, a (write) in application systems, either a real 8-bit bus (with 8-bit address) is used or port 2 serves as page register which selects pages of 256-byte. however, the distinction, whether port 2 is used as general purpose i/o or as "page address" is made by the external system design. from the device? point of view it cannot be decided whether the port 2 data is used externally as address or as i/o data! hence, a special page register is implemented into the sab 80c515a to provide the possibility of accessing the xram also with the movx @ri instructions, i.e. xpage serves the same function for the xram as port 2 for external data memory.
sab 80c515a/83c515a-5 semiconductor group 16 special function register xpage the reset value of xpage is 00 h . xpage can be set and read by software. the register xpage provides the upper address byte for accesses to xram with movx @ri instructions. if the address formed from xpage and ri is less than the xram address range, then an external access is performed. for the sab 80c515a the contents of xpage must be greater or equal than f8 h in order to use the xram. of course, the xram must be enabled if it shall be used with movx @ri instructions. thus, the register xpage is used for addressing of the xram; additionally its contents are used for generating the internal xram select. if the contents of xpage is less than the xram address range then an external bus access is performed where the upper address byte is provided by p2 and not by xpage! therefore, the software has to distinguish two cases, if the movx @ri instructions with paging shall be used: a) access to xram: the upper address byte must be written to xpage or p2; both writes selects the xram address range. b) access to external memory: the upper address byte must be written to p2; xpage will be loaded with the same address in order to deselect the xram. addr. 91 h xpage
sab 80c515a/83c515a-5 semiconductor group 17 control of xram in the sab 80c515a there are two control bits in register syscon which control the use and the bus operation during accesses to the additional on-chip ram (xram). special function register syscon reset value of syscon is xxxx xx01b. the control bit xmap0 is a global enable/disable bit for the additional on-chip ram (xram). if this bit is set, the xram is disabled, all movx accesses use external memory via the external bus. in this case the sab 80c515a does not use the additional on-chip ram and is compatible with the types without xram. addr. 0b1 h xmap1 xmap0 syscon bit function xmap0 global enable/disable bit for xram memory. xmap0 =0: the access to xram (= on-chip xdata memory) is en- abled. xmap0 = 1: the access to xram is disabled. all movx accesses are performed by the external bus (reset state). xmap1 control bit for / rd/wr signals during accesses to xram; this bit has no effect if xram is disabled (xmap0 = 1) or if addresses exceeding the xram address range are used for movx accesses. xmap1 = 0: the signals rd and wr are not activated during accesses to xram. xmap1 = 1: the signals rd and wr are activated during accesses to xram.
sab 80c515a/83c515a-5 semiconductor group 18 xmap0 is hardware protected by an unsymmetric latch. an unintentional disabling of xram could be dangerous since indeterminate values would be read from external bus. to avoid this the xmap-bit is forced to '1' only by reset. additionally, during reset an internal capacitor is loaded. so after reset state xram is disabled. because of the load time of the capacitor xmap0-bit once written to '0' (that is, discharging capacitor) cannot be set to '1' again by software. on the other hand any distortion (software hang up, noise, ...) is not able to load this capacitor, too. that is, the stable status is xram enabled. the only way to disable xram after it was enabled is a reset. the clear instruction for xmap0 should be integrated in the program initialization routine before xram is used. in extremely noisy systems the user may have redundant clear instructions. the control bit xmap1 is relevant only if the xram is accessed. in this case the external rd and wr signals at p3.6 and p3.7 are not activated during the access, if xmap1 is cleared. for debug purposes it might be useful to have these signals and the addresses at ports 0.2 available. this is performed if xmap1 is set. the behaviour of port 0 and p2 during a movx access depends on the control bits in register syscon and on the state of pin ea . the table 1 lists the various operating conditions. it shows the following characteristics: a) use of p0 and p2 pins during the movx access. bus: the pins work as external address/data bus. if (internal) xram is accessed, the data written to the xram can be seen on the bus in debug mode. i/0: the pins work as input/output lines under control of their latch. b) activation of the rd and wr pin during the access. c) use of internal or external xdata memory. the shaded areas describe the standard operation as each 80c51 device without on-chip xram behaves.
sab 80c515a/83c515a-5 semiconductor group 19 table 1: behaviour of p0/p2 and rd / wr during movx accesses 00 10 x1 dptr < xram address range movx @ri movx @dptr a) p0/p2 y bus b) rd / wr active c) ext. memory is used a) p0/p2 y bus b) rd / wr active c) ext. memory is used a) p0/p2 y bus b) rd / wr active c) ext. memory is used a) p0/p2 y bus b) rd / wr active c) ext. memory is used a) p0/p2 y bus b) rd / wr active c) ext. memory is used a) p0/p2 y bus b) rd / wr active c) ext. memory is used a) p0/p2 y bus b) rd / wr active c) ext. memory is used a) p0/p2 y bus b) rd / wr active c) ext. memory is used modes compatible to 8051 - family 00 10 x1 xmap1, xmap0 ea = 0 a) p0/p2 y bus ( wr -data only) b) rd / wr inactive c) xram is used a) p0/p2 y bus ( wr -data only) b) rd / wr active c) xram is used a) p0/p2 y i/0 b) rd / wr inactive c) xram is used a) p0/p2 y bus ( wr -data only) b) rd / wr active c) xram is used a) p0/p2 y bus ( wr -data only) p2 y i/0 b) rd / wr inactive c) xram is used a) p0/p2 y bus ( wr -data only) p2 y i/0 b) rd / wr active c) xram is used a) p0 y bus p2 y i/0 b) rd / wr active c) ext. memory is used a) p0/p2 y i/0 b) rd / wr inactive c) xram is used a) p0 y bus ( wr -data only) p2 y i/0 b) rd / wr active c) xram is used a) p0 y bus p2 y i/0 b) rd / wr active c) ext. memory is used a) p0 y bus p2 y i/0 b) rd / wr active c) ext. memory is used a) p0 y bus p2 y i/0 b) rd / wr active c) ext. memory is used a) p0 y bus p2 y i/0 b) rd / wr active c) ext. memory is used a) p0 y bus p2 y i/0 b) rd / wr active c) ext. memory is used a) p0 y bus p2 y i/0 b) rd / wr active c) ext. memory is used dptr 3 xram address range xpage < xram addr. page range xpage 3 xram addr. page range xmap1, xmap0 ea = 1 a) p0 y bus p2 y i/0 b) rd / wr active c) ext. memory is used
sab 80c515a/83c515a-5 semiconductor group 20 special function registers all registers, except the program counter and the four general purpose register banks, reside in the special function register area. the special function registers include arithmetic registers, pointers, and registers that provide an interface between the cpu and the on-chip peripherals. there are also 128 directly addressable bits within the sfr area. all special function registers are listed in table 2 and table 3. in table 2 they are organized in numeric order of their addresses. in table 3 they are organized in groups which refer to the functional blocks of the sab 80c515a. table 2 special function register address register contents after reset address register contents after reset 80 h 81 h 82 h 83 h 84 h 85 h 86 h 87 h p0 1) sp dpl dph (wdtl) (wdth) wdtrel pcon 0ff h 07 h 00 h 00 h 00 h 00 h 98 h 99 h 9a h 9b h 9c h 9d h 9e h 9f h s0con 1) sbuf reserved reserved reserved reserved reserved reserved 00 h xx h 2) xx h 2) xx h 2) xx h 2) xx h 2) xx h 2) xx h 2) 88 h 89 h 8a h 8b h 8c h 8d h 8e h 8f h tcon 1) tmod tl0 tl1 th0 th1 reserved reserved 00 h 00 h 00 h 00 h 00 h 00 h xx h 2) xx h 2) a0 h a1 h a2 h a3 h a4 h a5 h a6 h a7 h p2 1) reserved reserved reserved reserved reserved reserved reserved 0ff h xx h 2) xx h 2) xx h 2) xx h 2) xx h 2) xx h 2) xx h 2 90 h 91 h 92 h 93 h 94 h 95 h 96 h 97 h p1 1) xpage reserved reserved reserved reserved reserved reserved 0ff h xx h 2) xx h 2) xx h 2) xx h 2) xx h 2) xx h 2) xx h 2) a8 h a9 h aa h ab h ac h ad h ae h af h ien0 1) ip0 srell reserved reserved reserved reserved reserved 00 h 00 h 0d9 h xx h 2) xx h 2) xx h 2) xx h 2) xx h 2) 1) bit-addressable special function registers 2) x means that the value is indeterminate and the location is reserved
sab 80c515a/83c515a-5 semiconductor group 21 table 2: special function register (cont?) address register contents after reset address register contents after reset b0 h b1 h b2 h b3 h b4 h b5 h b6 h b7 h p3 1) syscon reserved reserved reserved reserved reserved reserved 0ff h xxxx xx01 b 2) xx h 2) xx h 2) xx h 2) xx h 2) xx h 2) xx h 2 d0 h d1 h d2 h d3 h d4 h d5 h d6 h d7 h psw 1) reserved reserved reserved reserved reserved reserved reserved 00 h xx h 2) xx h 2) xx h 2) xx h 2) xx h 2) xx h 2) xx h 2) b8 h b9 h ba h bb h bc h bd h be h bf h en1 1) ip1 srelh reserved reserved reserved reserved reserved 00 h xx00 0000 b 2) xxxx xx11 b 2) xx h 2) xx h 2) xx h 2) xx h 2 xx h 2) d8 h d9 h da h db h dv h dd h de h df h adcon0 1) addath addatl p6 adcvon1 reserved reserved reserved 00 h 00 h 00 h xx h 2) xxxx 0000 b 2) xx h 2) xx h 2) xx h 2) c0 h c1 h c2 h c3 h c4 h c5 h c6 h c7 h ircon 1) ccen ccl1 cch1 ccl2 cch2 ccl3 cch3 00 h 00 h 00 h 00 h 00 h 00 h 00 h 00 h e0 h e1 h e2 h e3 h e4 h e5 h e6 h e7 h acc 1) reserved reserved reserved reserved reserved reserved reserved 00 h xx h 2) xx h 2) xx h 2) xx h 2) xx h 2) xx h 2) xx h 2) c8 h c9 h ca h cb h cc h cd h ce h cf h t2con 1) reserved crcl crch tl2 th2 reserved reserved 00 h xx h 2) 00 h 00 h 00 h 00 h xx h 2) xx h 2 e8 h e9 h ea h eb h ec h ed h ee h ef h p4 1) reserved reserved reserved reserved reserved reserved reserved 0ff h xx h 2) xx h 2) xx h 2) xx h 2) xx h 2) xx h 2) xx h 2) 1) bit-addressable special function registers 2) x means that the value is indeterminate and the location is reserved
sab 80c515a/83c515a-5 semiconductor group 22 f0 h f1 h f2 h f3 h f4 h f5 h f6 h f7 h b 1) reserved reserved reserved reserved reserved reserved reserved 00 h xx h 2) xx h 2) xx h 2) xx h 2) xx h 2) xx h 2) xx h 2 f8 h f9 h fa h fb h fc h fd h fe h ff h p5 1) reserved reserved 00f h xx h 2) xx h 2) 1) bit-addressable special function registers 2) x means that the value is indeterminate and the location is reserved table 2: special function register (cont?) address register contents after reset address register contents after reset
sab 80c515a/83c515a-5 semiconductor group 23 table 3 special function registers - functional blocks block symbol name address contents after reset cpu acc b dph dpl psw sp accumulator b-register data pointer, high byte data pointer, low byte program status word register stack pointer 0e0 h 1) 0f0 h 1) 83 h 82 h 0d0 h 1) 81 h 00 h 00 h 00 h 00 h 00 h 07 h a/d- converter adcon0 adcon1 addath addatl a/d converter control register 0 a/d converter control register 1 a/d converter data reg. high byte a/d converter data reg. low byte 0d8 h 1) 0dc h 0d9 h 0da h 00 h 0xxx 0000 b 3) 00 h 00 h interrupt system en0 ien1 ip0 ip1 ircon0 tcon 2) t2con 2) interrupt enable register 0 interrupt enable register 1 interrupt priority register 0 interrupt priority register 1 interrupt request control register timer control register timer 2 control register 0a8 h 1) 0b8 h 1) 0a9 h 0b9 h 0c0 h 1) 88 h 1) 0c8 h 00 h 00 h 00 h xx00 0000 b 00 h 00 h 00 h compare/ capture- unit (ccu) ccen cch1 cch2 cch3 ccl1 ccl2 ccl3 crch crcl th2 tl2 t2con comp./capture enable reg. comp./capture reg. 1, high byte comp./capture reg. 2, high byte comp./capture reg. 3, high byte comp./capture reg. 1, low byte comp./capture reg. 2, low byte comp./capture reg. 3, low byte com./rel./capt. reg. high byte com./rel./capt. reg. low byte timer 2, high byte timer 2, low byte timer 2 control register 0c1 h 0c3 h 0c5 h 0c7 h 0c2 h 0c4 h 0c6 h 0cb h 0ca h 0cd h 0cc h 0c8 h 1) 00 h 00 h 00 h 00 h 00 h 00 h 00 h 00 h 00 h 00 h 00 h 00 h xram xpage syscon page address register for exten- ded on chip ram xram control register 91 h 0b1 h 00 h xxxx xx01 b 3) 1) bit-addressable special function registers 2) this special function register is listed repeatedly since some bits of it also belong to other functional blocks. 3) x means that the value is indeterminate and the location is reserved
sab 80c515a/83c515a-5 semiconductor group 24 table 3 special function registers - functional blocks (cont?) block symbol name address contents after reset ports p0 p1 p2 p3 p4 p5 p6 port 0 port 1 port 2 port 3 port 4 port 5 port 6, analog/digital input 80 h 1) 90 h 1) 0a0 h 1) 0b0 h 1) 0e8 h 1) 0f8 h 1) 0db h 0ff h 0ff h 0ff h 0ff h 0ff h 0ff h pow.sav.m ode pcon power control register 87 h 00 h serial channels adcon0 2) pcon 2) sbuf scon srell srelh a/d converter control reg. power control register serial channel buffer reg. serial channel control reg. serial channel reload reg., low byte serial channel reload reg., high byte 0d8 h 1) 87 h 99 h 98 h 1) aa h ba h 00 h 00 h 0xx h 3) 00 h d9 h xxxx xx11 b 3) timer 0/ timer 1 tcon th0 th1 tl0 tl1 tmod timer control register timer 0, high byte timer 1, high byte timer 0, low byte timer 1, low byte timer mode register 88 h 1) 8c h 8d h 8a h 8b h 89 h 00 h 00 h 00 h 00 h 00 h 00 h watchdog ien0 2) ien1 2) ip0 2) ip1 2) wdtrel interrupt enable register 0 interrupt enable register 1 interrupt priority register 0 interrupt priority register 1 watchdog timer reload reg. 0a8 h 1) 0b8 h 1) 0a9 h 0b9 h 86 h 00 h 00 h 00 h xx00 0000 b 00 h 1) bit-addressable special function registers 2) this special function register is listed repeatedly since some bits of it also belong to other functional blocks. 3) x means that the value is indeterminate and the location is reserved
sab 80c515a/83c515a-5 semiconductor group 25 a/d converter in the sab 80c515a a new high performance / high-speed 8-channel 10-bit a/d-converter (adc) is implemented. its successive approximation technique provides 7 m s conversion time ( f osc = 16 mhz). the conversion principle is upward compatible to the one used in the sab 80c515. the main functional blocks are shown in figure 3. the comparator is a fully differential comparator for a high power supply rejection ratio and very low offset voltages. the capacitor network is binary weighted providing genuine10-bit resolution. the table below shows the sample time t s and the conversion time t c , which are dependend on f osc and a new prescaler. the adc is clocked ( f adc ) with f osc /8. because of the adc's maximum clock frequency of 2 mhz the prescaler (divide-by-2) has to be enabled (set bit adcl in sfr adcon 1) when the oscillator frequency ( f osc ) is higher than 16 mhz. f osc [mhz] prescaler f adc [mhz] sample time t s [ m s] conversion time (incl. sample time) t c [ m s] 12 ? 8 1.5 2.67 9.3 ? 16 0.75 5.33 18.66 16 ? 8 2.0 2.0 7.0 ? 16 1.0 1.0 14.0 18 ? 8 ? ? ? 16 1.125 3.55 12.4
sab 80c515a/83c515a-5 semiconductor group 26 figure 3 block diagram a/d converter
sab 80c515a/83c515a-5 semiconductor group 27 timers /counters the sab 80c515a contains three 16-bit timers/counters wich are useful in many applications for timing and counting. the input clock for wach timer/counter is 1/12 of the oscillator frequency in the timer operation or can be taken from an external clock source for the counter operation (maximum count rate is 1/24 of the oscillator frequency). timer/counter 0 and 1 these timers/counters can operate in four modes: mode 0: 8-bit timer/counter with 32:1 prescaler mode 1: 16-bit timer/counter mode 2: 8-bit timer/counter with 8-bit auto-reload mode 3: timer/counter 0 is configured as one 8-bit timer/counter and one 8-bit timer; timer/counter 1 in this mode holds its count. external inputs into and int1 can be programmed to function as a gate for timer/counters 0 and 1 to facilitate pulse width measurements. timer/counter 2 timer/counter 2 of the sab 80c515a is a 16-bit timer/counter with several additional features. it offers a 2:1 prescaler, a selectable gate function, and compare, capture and reload functions. corresponding to the 16-bit timer register there are four 16-bit capture/compare registers, one of them can be used to perform a 16-bit reload on a timer overflow or external event. each of these registers corresponds to a pin of port 1 for capture input/compare output. figure 4 shows a block diagram of timer/counter 2. reload a 16-bit reload can be performed with the 16-bit crc register consisting of crcl and crch. there are two modes from which to select: mode 0: reload is caused by a timer 2 overflow (auto-reload). mode 1: reload is caused in response to a negative transition at pin t2ex (p1.5), which can also request an interrupt.
sab 80c515a/83c515a-5 semiconductor group 28 capture this feature permits saving of the actual timer/counter contents into a selected register upon an external event or a software write operation. two modes are provided to latch the current 16-bit value of timer 2 registers tl2 and th2 into a dedicated capture register. mode 0: capture is performed in response to a transition at the corresponding port 1 pins cc0 to cc3. mode 1: write operation into the low-order byte of the dedicated capture register causes the timer 2 contents to be latched into this register. compare in compare mode, the 16-bit values stored in the dedicated compare registers are compared to the contents of the timer 2 registers. if the count value in the timer 2 registers matches one of the stored values, an appropriate output signal is generated and an interrupt is requested. two compare modes are provided: mode 0: upon a match the output signal changes from low to high. it goes back to low level when timer 2 overflows. mode 1: the transition of the output signal can be determined by software. a timer 2 overflow causes no output change.
sab 80c515a/83c515a-5 semiconductor group 29 figure 4 block diagram of timer/counter 2
sab 80c515a/83c515a-5 semiconductor group 30 interrupt structure the sab 80c515a has 12 interrupt vectors with the following vector addresses and request flags. each interrupt vector can be individually enabled/disabled. the minimum response time to an interrupt request is more than 3 machine cycles and less than 9 machine cycles, if no other interrrupt of the same or a higher priority level is in process. figure 5 shows the interrupt request sources. external interrupts 0 and 1 can be activated by a low-level or a negative transition (selectable) at their corresponding input pin, external interrupts 2 and 3 can be programmed for triggering on a negative or a positive transition. the external interrupts 3 or 6 are combined with the corresponding alternate functions compare (output) and capture (input) on port 1. for programming of the priority levels the interrupt vectors are combined to pairs. each pair can be programmed individually to one of four priority levels by setting or clearing one bit in special function register ip0 and one in ip1. figure 6 shows the priority level structure. table 4 interrupt sources and vectors source (request flags) vector address vector ie0 tf0 ie1 tf1 ri + ti tf2 + exf2 iadc iex2 iex3 iex4 iex5 iex6 0003 h 000b h 0013 h 001b h 0023 h 002b h 0043 h 004b h 0053 h 005b h 0063 h 006b h external interrupt 0 timer 0 interrupt external interrupt 1 timer 1 interrupt serial port interrupt timer 2 interrupt a/d converter interrupt external interrupt 2 external interrupt 3 external interrupt 4 external interrupt 5 external interrupt 6
sab 80c515a/83c515a-5 semiconductor group 31 figure 5 interrupt request sources
sab 80c515a/83c515a-5 semiconductor group 32 figure 6 interrupt priority level structure
sab 80c515a/83c515a-5 semiconductor group 33 i/o ports the sab 80c515a has six 8-bit i/o ports and one input port. port 0 is an open-drain bidirectional i/o port, while ports 1 to 5 are quasi-bidirectional i/o ports with internal pull-up resistors. that means, when configured as inputs, ports 1 to 5 will be pulled high and will source current when externally pulled low. port 0 will float when configured as input. port 0 and port 2 can be used to expand the program and data memory externally. during an access to external memory, port 0 emits the low-order address byte and reads/writes the data byte, while port 2 emits the high-order address byte. in this function, port 0 is not an open-drain port, but uses a strong internal pull-up fet. ports 1, 3 and 4 are provided for several alternate functions, as listed below: the sab 80c515a has one dual-purpose input port. the anx lines of port 6 in the sab 80c515 can individually be used as analog or digital inputs. reading the special function register p6 allows the user to input the digital values currently applied to the port pins. it is not necessary to select these modes by software; the voltages applied at port 6 pins can be converted to digital values using the a/d converter and at the same time the pins can be read via sfr p6. it must be noted, however, that the results in port p6 bits will be indeterminate if the levels at the corresponding pins are not within their v il / v ih specifications. furthermore, it is not possible to use port p6 as an output port. special function register p6 is located at address 0db h . in hardware power down mode the port pins and several control lines enter a floating state. for more details see the section about hardware power down mode. port symbol function p1.0 p1.1 p1.2 p1.3 p1.4 p1.5 p1.6 p1.7 p3.0 p3.1 p3.2 p3.3 p3.4 p3.5 p3.6 p3.7 p4.0 int3 /cc0 int4/cc1 int5/cc2 int6/cc3 int2 t2ex clkout t2 rxd txd int0 int1 t0 t1 wr rd adst external interrupt 3 input, compare 0 output, capture 0 input external interrupt 4 input, compare 1 output, capture 1 input external interrupt 5 input, compare 2 output, capture 2 input external interrupt 6 input, compare 3 output, capture 3 input external interrupt 2 input timer 2 external reload trigger input system clock output timer 2 external count or gate input serial port? receiver data input (asynchronous) or data input /output (synchronous) serial port? transmitter data output (asynchronous) or clock output (synchronous) external interrupt 0 input, timer 0 gate control external interrupt 1 input, timer 1 gate control timer 0 external counter input timer 1 external counter input external data memory write strobe external data memory read strobe a/d converter, external start of conversion
sab 80c515a/83c515a-5 semiconductor group 34 power saving modes the sab 80c515a provides ?due to siemens acmos technology ?four modes in which power consumption can be significantly reduced. the slow down mode the controller keeps up the full operating functionality, but is driven with one eight of its normal operating frequency. slowing down the frequency remarkable reduces power consumption. the idle mode the cpu is gated off from the oscillator, but all peripherals are still supplied with the clock and continue working. the software power down mode operation of the sab 80c515a is stopped, the on-chip oscillator and the rc-oscillator are turned off. this mode is used to save the contents of the internal ram with a very low standby current and is fully compatible to the power down mode of the sab 80c515. the hardware power down mode operation of the sab 80c515a is stopped, the on-chip oscillator and the rc-oscillator are turned off. the pin hwpd controls this mode. port pins and several control lines enter a floating state. the hardware power down mode is new in the sab 80c515a and is independent of the state of pin pe /swd (which enables only the software initiated power reduction modes). hardware enable for software controlled power saving modes a dedicated pin pe /swd of the sab 80c515a allows to block the software controlled power saving modes. since this pin is mostly used in noise-critical application it is combined with an automatic start of the watchdog timer. pe /swd = v ih (logic high level): using of the power saving modes is not possible. the watchdog timer starts immediately after reset. the instruction sequences used for entering of power saving modes will not affect the normal operation of the device. pe /swd = v il (logic low level): all power saving moes can be activated by software. the watchdog timer can be started by software at any time. when left unconnected, pin pe /swd is pulled high by a weak internall pull-up. this is done to provide system protection on default. the logic-level applied to pin pe /swd can be changed during program execution to allow or to block the use of the power saving modes without any effect on the on-chip watchdog circuitry.
sab 80c515a/83c515a-5 semiconductor group 35 requirements for hardware power down mode there is no dedicated pin to enable the hardware power down mode. the control pin pe /swd has no control function in this mode. it enables and disables only the use of software controlled power saving modes. software controlled power saving modes all of these modes are entered by software. special function register pcon (power control register, address is 87 h ) is used to select one of these modes. slow down mode during slow down operation all signal frequencies that are derived from the oscillator clock, are divided by eight, also the clockout signal and and the watchdog timer count. the slow down mode is enabled by setting bit sd. the controller actually enters the slow down mode after a short synchronisation period (max. 2 machine cycles). the slow down mode is disabled by clearing bit sd. idle mode during idle mode all peripherals of the sab 80c515a (except for the watchdog timer) are still supplied by the oscillator clock. thus the user has to take care which peripheral should continue to run and which has to be stopped during idle. the procedure to enter the idle mode is similar to the one entering the power down mode. the two bits idle and idls must be set by two consecutive instructions to minimize the chance of unintentional activating of the idle mode. there are two ways to terminate the idle mode: the idle mode can be terminated by activating any enabled interrupt. this interrupt will be serviced and the instruction to be executed following the reti instruction will be the one following the instruction that set the bit idls. the other way to terminate the idle mode, is a hardware reset. since the oscillator is still running, the hardware reset must be held active only for two machine cycles for a complete reset. normally the port pins hold the logical state they had at the time idle mode was activated. if some pins are programmed to serve their alternate functions they still continue to output during idle mode if the assigned function is on. the control signals ale and psen hold at logic high levels (see table 5).
sab 80c515a/83c515a-5 semiconductor group 36 software power down mode the power down mode is entered by two consecutive instructions directly following each other. the first instruction has to set the flag pde (power down enable) and must not set pds (power down set). the following instruction has to set the start bit pds. bits pde and pds will automatically be cleared after having been set. the instruction that sets bit pds is the last instruction executed before going into power down mode. the only exit from power down mode is a hardware reset. the status of all output lines of the controller can be looked up in table 5. hardware controlled power down mode the pin hwpd controls this mode. if it is on logic high level (inactive) the part is running in the normal operating modes. if pin hwpd gets active (low level) the part enters the hardware power down mode; this is independent of the state of pin pe /swd. hwpd is sampled once per machine cycle. if it is found active, the device starts a complete internal reset sequence. the watchdog timer is stopped and its status flag wdts is cleared exactly the same effects as a hardware reset. in this phase the power consumption is not yet reduced. after completion of the internal reset both oscillators of the chip are disabled. at the same time the port pins and several control lines enter a floating state as shown in table 5. in this state the power consumption is reduced to the power down current ipd. also the supply voltage can be reduced. table 5 also lists the voltages which may be applied at the pins during hardware power down mode without affecting the low power consumption. termination of hwpd mode: this power down state is maintained while pin hwpd is held active. if hwpd goes to high level (inactive state) an automatic start up procedure is performed: first the pins leave their floating condition and enter their default reset state (as they had immediately before going to float state). both oscillators are enabled. the oscillator watchdog? rc oscillator starts up very fast (typ. less than 2 ms). because the oscillator watchdog is active it detects a failure condition if the on-chip oscillator hasn? yet started. hence, the watchdog keeps the part in reset and supplies the internal clock from the rc oscillator. finally, when the on-chip oscillator has started, the oscillator watchdog releases the part from reset with oscillator watchdog status flag set. when automatic start of the watchdog was enabled (pe /swd connected to v cc ), the watchdog timer will start, too (with its default reload value for time-out period). the reset pin overrides the hardware power down function, i.e. if reset gets active during hardware power down it is terminated and the device performs the normal resetfunction.(thus, pin reset has to be inactive during hardware power down mode). function.(thus, pin reset has to be inactive during hardware power down mode).
sab 80c515a/83c515a-5 semiconductor group 37 table 5 status of all pins during idle mode, power down mode and hardware power down mode pins idle mode last instruction executed from power down mode last instruction executed from hardware power down internal rom external rom internal rom external rom status p0 data ?at data ?at 1) p1 data alt outputs dat alt outputsa data last outputs data last outputs ?ating 1) p2 data address data data p3 data alt outputs data alt outputs data last output data last output outputs p4 data alt outputs data alt outputs data last outputs data last output disabled p5 data alt output data alt output data last output data last output input p6 1) 1) 1) 1) function ea active input 2) pe /swd active input pull-up disabled 2) xtal1 active output xtal2 disabled input function 1) psen high high low low ?ating output ale high high low low v aref v agnd active supply pins 3) reset active input must be high 1) applied voltage range at pin v ss v in v cc 2) v in = v ss or v in = v cc 3) v ss v in v cc ; v aref 3 v agnd
sab 80c515a/83c515a-5 semiconductor group 38 serial interface the sab 80c515a has a full duplex and receive buffered serial interface. it is functionally identical with the serial interface of the sab 8051. table 6 shows possible configurations and the according baud rates. table 6 baud rate generation mode mode 0 8-bit syn- chron- ous channel baud- rate f o s c =12 mhz f osc =16 mhz f osc =18 mhz 1 mhz 1.33 mhz 1.5 mhz derived from f os c mode mode 1 8-bit uart baud- rate f os c =12 mhz f osc =16 mhz f osc =18 mhz 1 baud ?62.5 kbaud 1 baud ?83 kbaud 1 baud ?93.7 kbaud 183 baud ?375 kbaud 244 baud ?500 kbaud 2375 baud ?562.5 kbaud derived from timer 1 10-bit baudrate generator mode mode 2 mode 3 9-bit uart baud- rate f osc = 12 mhz f osc =16 mhz f osc =18 mhz 187.5 kbaud/ 375 kbaud 250 baud/ 500 kbaud 281.2 kbaud/ 562.5 kbaud 1 baud ? 62.5 kbaud 1 baud ? 83.3 kbaud 1 baud ? 93.7 kbaud 183 baud ?5 kbaud 244 baud ?500 kbaud 275 baud ?562.5 kbaud derived from f osc/ 2 timer 1 10-bit baudrate generator
sab 80c515a/83c515a-5 semiconductor group 39 the serial interface can operate in 4 modes: mode 0: shift register mode: serial data enters and exits through r d. t d outputs the shift clock 8 data bits are transmitted/received (lsb first). the baud rate is fixed at 1/12 of the oscillator fre- quency. mode 1: 8-bit uart, variable baud rate: 10-bit are transmitted (through t d) or received (through r d): a start bit (0), 8 data bits (lsb first), and a stop bit (1). on reception, the stop bit goes into rb80 in special function register scon. the baud rate is variable. mode 2: 9-bit uart, fixed baud rate: 11-bit are transmitted (through t d) or received (through r d): a start bit (0), 8 data bits (lsb first), a programmable 9th, and a stop bit (1). on transmission, the 9th data bit (tb80 in scon) can be assigned to the value of 0 or 1. for example, the par- ity bit (p in the psw) could be moved into tb80 or a second stop bit by setting tb80 to 1. on reception the 9th data bit goes into rb80 in special function register scon, while the stop bit is ignored. the baud rate is programmable to either 1/32 or 1/64 of the oscillator frequency. mode 3: 9-bit uart, variable baud rate: 11-bit are transmitted (through t d) or received (through r d): a start bit (0), 8 data bits (lsb first), a programmable 9th, and a stop bit (1). in fact, mode 3 is the same as mode 2 in all respects except the baud rate. the baud rate in mode 3 is vari- able. variable baud rates for serial interface variable baud rates for modes 1 and 3 of serial interface can be derived from either timer 1 or a new dedicated baudrate generator. the baud rate is generated by a free running 10-bit timer with programmable reload register. the default value after reset in the reload registers srell and srelh provides a baud rate of 4.8 kbaud (smod = 0) or 9.6 kbaud (smod = 1) at 12 mhz oscillator frequency. this guaran- tees full compatibility to the sab 80c515. mode 1.3 baud rate = 2 smod * f osc 64 * (2 10 - srel)
sab 80c515a/83c515a-5 semiconductor group 40 fail safe units the sab 80c515a offers enhanced fail safe mechanisms, which allow an automatic recovery from software upset or hardware failure: ? a programmable watchdog timer (wdt), with variable time-out period from 512 m s up to appr. 1.1 s @12 mhz. upward compatible to sab 80c515 watchdog timer. ? an oscillator watchdog (owd) which monitors the on-chip oscillator and forces the microcontroller into reset state, in case the on-chip oscillator fails; it also controls the restart from the hardware power down mode and provides the clock for a fast internal reset after power-on. programmable watchdog timer the wdt can be activated by hardware or software. hardware initialization is done when pin pe /swd (pin 4) is held high during reset. the sab 80c515a then starts program execution with the wdt running. since pin pe /swd is only sampled during reset, the wdt cannot be started externally during normal operation. software initialization is done by setting bit swdt in sfr ien1. a refresh of the watchdog timer is done by setting bits wdt (sfr ien0) and swdt consecutively. this double instruction sequence has been implemented to increase system security. when a watchdog timer reset occurs, the watchdog timer keeps on running, but a status flag wdts (sfr ip0) is set. this flag can also be cleared by software. figure 7 shows the block diagram of the programmable watchdog timer. oscillator watchdog the unit serves three functions: ? monitoring of the on-chip oscillator? function. the watchdog monitors the on-chip oscillator? frequency; if it is lower than the frequency of the auxiliary rc oscillator in the watchdog unit, the internal clock is supplied by the rc oscillator and the device is forced into reset; if the failure condition disappears (i.e. the on- chip oscillator has again a higher frequency than the rc oscillator), the part executes a final reset phase of appr. 0.25 ms in order to allow the oscillator to stabilize; then the oscillator watchdog reset is released and the part starts program execution again. ? restart from the hardware power down mode. if the hardware power down mode is terminated the oscillator watchdog has to control the correct start-up of the on-chip oscillator and to restart the program. the oscillator watchdog function is only part of the complete hardware power down sequence; however, the watchdog works identically to the monitoring function. ? fast internal reset after power-on. in this function the oscillator watchdog unit provides a clock supply for the reset before the on-chip oscillator has started. in this case the oscillator watchdog unit also works identically to the monitoring function.
sab 80c515a/83c515a-5 semiconductor group 41 figure 8 shows the block diagram of the oscillator watchdog unit. it consists of an internal rc oscillator which provides the reference frequency for the frequency comparator. figure 7 block diagram of the programmable watchdog timer figure 8 functional block diagram of the oscillator watchdog
sab 80c515a/83c515a-5 semiconductor group 42 fast internal reset after power-on the sab 80c515a can use the oscillator watchdog unit for a fast internal reset procedure after power-on. normally members of the 8051 family (like the sab 80c515) enter their default reset state not before the on-chip oscillator starts. the reason is that the external reset signal must be internally synchronized and processed in order to bring the device into the correct reset state. especially if a crystal is used the start up time of the oscillator is relatively long (typ. 1 ms). during this time period the pins have an undefined state which could have severe effects e.g. to actuators connected to port pins. in the sab 80c515a the oscillator watchdog unit avoids this situation. after power-on the oscillator watchdog? rc oscillator starts working within a very short start-up time (typ. less than 2 ms). in the following the watchdog circuitry detects a failure condition for the on-chip oscillator because this has not yet started (a failure is always recognized if the watchdog? rc oscillator runs faster than the on-chip oscillator). as long as this condition is valid the watchdog uses the rc oscillator output as clock source for the chip rather than the on-chip oscillator? output. this allows correct resetting of the part and brings also all ports to the defined state. delay time between power-on and correct reset state: typ.: 18 m s max.: 34 m s instruction set the sab 80c515a / 83c515a-5 has the same instruction set as the industry standard 8051 microcontroller. a pocket guide is available which contains the complete instruction set in functional and hexadecimal order. furtheron it provides helpful information about special function registers, interrupt vectors and assembler directives. literature information title ordering no. microcontroller family sab 8051 pocket guide b158-h6497-x-x-7600
sab 80c515a/83c515a-5 semiconductor group 43 absolute maximum ratings ambient temperature under bias ?40 to 85 ?c storage temperature ?65 to 150 ?c voltage on v cc pins with respect to ground ( v ss ) 0.5 v to 6.5 v voltage on any pin with respect to ground ( v ss ) ?0.5 to v cc + 0.5 v input current on any pin during overload condition ?10ma to + 10 ma absolute sum of all input currents during overload condition |100 ma| power dissipation 1 w note stresses above those listed under "absolute maximum ratings" may cause permanent damage of the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for longer periods may affect device reliability. during overload conditions (v in > v cc or v in < v ss ) thevoltage on v cc pins with respect to ground (v ss ) must not exeed the values defind- ed by the absolute maximum ratings. dc characteristics v cc = 5 v + 10 %, ?15 %; v ss = 0 v t a = 0 to 70 ?c for the sab 80c515a t a = 40 to 85 ?c for the sab 80c515a-t3 parameter symbol limit values unit test condition min. max. input low voltage (exept ea ,reset , hwpd ) v il ?0.5 0.2 v cc ?0.1 v input low voltage ea v i l 1 ?0.5 0.2 v cc ?0.3 v input low voltage (hwpd , reset ) v i l 2 ?0.5 0.2 v cc + 0.1 v input high voltage (exept reset , xtal2 and hwpd ) v ih 0.2 v cc + 0.9 v cc + 0.5 v input high voltage to xtal2 v ih1 0.7 v cc v cc + 0.5 v input high voltage to reset and hwpd v ih2 0.6 v cc v cc + 0.5 v
sab 80c515a/83c515a-5 semiconductor group 44 dc characteristics (cont?) parameter symbol limit values unit test condition min. max. output low voltage (ports 1, 2, 3, 4, 5) v ol ? 0.45 v i ol = 1.6 ma 1) output low voltage (ports 0, ale, reset ) v ol1 0.45 v i ol = 3.2 ma 1) output high voltage, (ports1, 2, 3, 4, 5) v oh 2.4 0.9 v c c ? ? v v i oh = ?80 m a i oh = ?10 m a output high voltage (port 0 in external bus mode,- ale, psen ) v oh 1 2.4 0.9 v c c ? ? v v i oh = ?800 m a i oh = ? 80 m a 2) logic 0 input current (ports 1, 2, 3, 4, 5) i il ?10 ?70 m a v in = 2 v logical 1-to-0 transition current, ports 1, 2, 3, 4, 5 i tl ?65 ?650 m a v in = 2 v input leakage current (port 0, ea , p6, hwpd ) i l i ? ? 100 150 na na 0.45 < v i n < v cc 0.45 < v i n < v cc t a > 100 ?c input low current to reset for reset i il2 ?10 ?100 m a v in = 0.45 v input low current (xtal2 ) i i l 3 ? ?15 m a v in = 0.45 v input low current (pe /swd) i i l 4 ? ?20 m a v in = 0.45 v pin capacitance c i o ?10 pf f c = 1 mhz, t a = 25 ?c power-supply current: active mode, 12 mhz 7) active mode, 18 mhz 7) idle mode, 12 mhz 7) idle mode, 18 mhz 7) slow down mode, 12 mhz slow down mode, 18 mhz power down mode i cc i cc i cc i cc i cc i cc i pd ? ? ? ? ? ? ? 26 35 11.8 14.2 9 10 50 ma ma ma ma ma ma m a v cc = 5 v 4) v cc = 5 v 4) v cc = 5 v 5) v cc = 5 v 5) v cc = 5 v 6) v cc = 5 v 6) v cc = 2 ... 5.5 v 3) notes see page 43.
sab 80c515a/83c515a-5 semiconductor group 45 notes for page 44: 1) capacitive loading on ports 0 and 2 may cause spurious noise pulses to be superimposed on the v ol of ale and ports 1, 3, 4 and 5. the noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operation. in the worst case (capacitive loading > 100 pf), the noise pulse on ale line may exceed 0.8 v. in such cases it may be desirable to qualify ale with a schmitt-trigger, or use an address latch with a schmitt-trigger strobe input. 2) capacitive loading on ports 0 and 2 may cause the v oh on ale and psen to momentarily fall below the 0.9 v cc specification when the address lines are stabilizing. 3) i pd (software power down mode) is measured under following conditions: ea = reset = v cc ; port0 = port6 = v cc ; xtal1 = n.c.; xtal2 = v ss ; pe /swd = v ss ; hwpd = v cc ; v agnd = v ss ; v aref = v cc ; all other pins are disconnected. i pd (hardware power down mode): independent of any particular pin connection. 4) i cc (active mode) is measured with: xtal2 driven with t clch , t chcl = 5 ns, v il = v ss + 0.5 v, v ih = v cc ?0.5 v; xtal1 = n.c.; ea = pe /swd = v cc ; port0 = port6 = v cc ; hwpd = v cc ; reset = v ss ; all other pins are disconnected. i cc would be slightly higher if a crystal oscillator is used (ap- pr. 1 ma). 5) i cc (idle mode) is measured with all output pins disconnected and with all peripherals dis- abled; xtal2 driven with t clch , t chcl = 5 ns, v il = v ss + 0.5 v, v ih = v cc ?0.5 v; xtal1 = n.c.; reset = v cc ; hwpd = v cc ; port0 = port6 = v cc ; ea = pe /swd = v ss; all other pins are disconnected; 6) i cc (slow down mode) is measured with all output pins disconnected and with all peripherals disabled; xtal2 driven with t clch , t chcl = 5 ns, v il = v ss + 0.5 v, v ih = v cc ?0.5 v; xtal1 = n.c.; reset = v cc ; hwpd = v cc ; port6 = v cc ; ea = pe /swd = v ss ; all other pins are disconnected; 7) i cc max at other frequencies is given by: active mode: i cc (max) = 1.5 * f osc + 8 idle mode: i cc (max)= 0.4 * f osc + 7 where f osc is the oscillator frequency in mhz. i cc values are given in ma and measured at v cc = 5 v.
sab 80c515a/83c515a-5 semiconductor group 46 a/d converter characteristics v cc = 5 v + 10 %, ?15 %; v ss = 0 v v aref = v cc 5 %; v agnd = v ss 0.2 v; t a = 0 to 70 ?c for the sab 80c515a/83c515a-5 t a = 40 to 85 ?c for the sab 80c515a-t3/83c515a-5-t3 parameter symbol limit values unit test condition min. typ. max. analog input capacitance c i 25 70 pf sample time (inc. load time) t s 4 t cy 1) m s 2) conversion time (inc. sample time) t c 14 t cy 1) m s 3) total unadjusted error tue 2 lsb v aref = v cc v agnd = v ss v aref supply current i ref 20 m a 1) t cy = (8*2 adcl ) / f osc ; ( t cy = 1/ f adc ; f adc = f osc /(8*2 adcl )) 2) this parameter specifies the time during the input capacitance c i, can be charged/discharged by the external source. it must be guaranteed, that the input capacitance c i, , is fully loaded within this time. 4tcy is 2 m s at the f osc = 16 mhz. after the end of the sample time t s , changes of the analog input voltage have no effect on the conversion result. 3) this parameter includes the sample time t s. 14tcy is 7 m s at f osc = 16 mhz.
sab 80c515a/83c515a-5 semiconductor group 47 ac characteristics v cc = 5 v + 10 %, ?15 %; v ss = 0 v t a = 0 to 70 ?c for the sab 80c515a/83c515a-5 t a = 40 to 85 ?c for the sab 80c515a-t3/83c515a-5-t3 ( c l for port 0, ale and psen outputs = 100 pf; c l for all other outputs = 80 pf) parameter symbol limit values unit 18 mhz clock variable clock 1/ t clcl = 3.5 mhz to 18 mhz min. max. min. max. program memory characteristics ale pulse width t lhll 71 ?2 t c lcl ?40 ? ns address setup to ale t avll 26 ? t c lcl ?30 ? ns address hold after ale t llax 26 ? t c lcl ?30 ? ns ale to valid instruction in t lliv 122 4 t c lcl ?100 ns ale to psen t llpl 31 t c lcl ?25 ns psen pulse width t plph 132 3 t c lcl ?35 ns psen to valid instruction in t pliv ?2 3 t c lcl ?75 ns input instruction hold after psen t pxix 0? ns input instruction float after psen t pxiz *) ?6 t c lcl ?10 ns address valid after psen t pxav *) 48 t c lcl ?8 ns address to valid instruction in t aviv 218 5 t c lcl 60 ns address float to psen t a zpl 0? ns *) interfacing the sab 80c515a to devices with float times up to 45 ns is permissible. this limited bus contention will not cause any damage to port 0 drivers.
sab 80c515a/83c515a-5 semiconductor group 48 ac characteristics (cont?) parameter symbol limit values unit 18 mhz clock variable clock 1/ t clcl = 3.5 mhz to 18 mhz min max. min. max. external data memory characteristics rd pulse width t rlrh 233 ?6 t clcl ? 100 ? ns wr pulse width t wlwh 233 ?6 t clcl ? 100 ? ns address hold after ale t llax2 81 ? 2 t clcl ? 30 ? ns rd to valid data in t rldv ?128 ? 5 t clcl ?150 ns data hold after rd t rhdx 0 0 ? ns data float after rd t rhdz ?51 2 t clcl ?60 ns ale to valid data in t lldv ?294 ? 8 t clcl ?150 ns address to valid data in t avdv ?335 ? 9 t clcl ?165 ns ale to wr or rd t llwl 117 217 3 t clcl ?50 3 t clcl + 50 ns wr or rd high to ale high t whlh 16 96 t clcl ?40 t clcl + 40 ns address valid to wr t avwl 92 ?4 t clcl ?130 ? ns data valid to wr transition t qvwx 11 ? t clcl ?45 ? ns data setup before wr t qvwh 239 ? 7 t clcl 150 ? ns data hold after wr t whqx 16 ? t clcl ?40 ? ns address float after rd t rlaz ?0 ? 0ns
sab 80c515a/83c515a-5 semiconductor group 49 program memory read cycle data memory read cycle
sab 80c515a/83c515a-5 semiconductor group 50 data memory write cycle
sab 80c515a/83c515a-5 semiconductor group 51 ac characteristics (cont'd) external clock cycle parameter symbol limit values unit variable clock frequ. = 3.5 mhz to 18 mhz min. max. external clock drive oscillator period t clcl 55.6 285 ns high time t chcx 20 t clcl- t clcx ns low time t clcx 20 t clcl- t chcx ns rise time t clch ? 20 ns fall time t chcl ? 20 ns oscillator frequency 1/ t clc 3.5 18 mhz
sab 80c515a/83c515a-5 semiconductor group 52 system clock timing ac characteristics (cont?) parameter symbol limit values unit 18 mhz clock variable clock 1/ t clcl = 3.5 mhz to 18 mhz min. max. min. max. system clock timing ale to clkout t llsh 349 7 t clcl ?40 ns clkout high time t shsl 71 2 t clcl ?40 ns clkout low time t slsh 516 10 t clcl ?40 ns clkout low to ale high t sllh 16 96 t clcl ?40 t clcl + 40 ns
sab 80c515a/83c515a-5 semiconductor group 53 rom verification characteristics t a = 25 ?c 5 ?c; v cc = 5 v + 10 %, ? 15 %; v ss = 0 v rom verification mode 1 parameter symbol limit values unit min. max. rom verification mode 1 (standard verify mode for not read protected rom) address to valid data t avqv ? 48 t clcl ns enable to valid data t elqv ? 48 t clcl ns data float after enable t ehoz 048 t clcl ns oscillator frequency 1/ t clcl 4 6 mhz
sab 80c515a/83c515a-5 semiconductor group 54 rom verification mode 2 (new verify mode for protected and not protected rom) rom verification mode 2
sab 80c515a/83c515a-5 semiconductor group 55 application example for verifying the internal rom with rom verify mode 2
sab 80c515a/83c515a-5 semiconductor group 56 ac testing: input, output waveforms ac testing: float waveforms recommended oscillator circuits ac inputs during testing are driven at v cc - 0.5 v for a logic ??and 0.45 v for a logic ?? timing measure- ments are made at v ihmin for a logic ??and v ilmax for a logic ?? for timing purposes a port pin is no longer floating when a 100 mv change from load voltage occurs and begins to float when a 100 mv change from the loaded v oh / v ol level occurs. i ol / i oh 3 20 ma.

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